1. Technical Field
The present disclosure relates to a semiconductor device and to a method of fabricating the same, and more particularly, to a semiconductor device having a buried gate electrode and to a method of fabricating the same.
2. Description of Related Art
Driven by an increased demand for highly integrated semiconductor devices, extensive research has been conducted into minimizing the areas of components such as, for example, transistors. With the downscaling of a transistor, the channel length and the channel width may also need to be decreased as well. However, a reduction in effective channel width may also lead to a drop in channel current, thereby lowering the current driving capability of the transistor. Also, a reduction in effective channel length may cause not only an increase in the channel current but may also lead to other difficulties, such as, for example, a short channel effect.
A recess-channel metal oxide semiconductor field effect transistor (MOSFET) has been proposed to overcome the short channel effect and downscale the transistor. The recess-channel MOSFET includes a recessed channel region and an insulated gate electrode. The insulated gate electrode is disposed on the recessed channel region. Thus, the recess-channel MOSFET can have a larger effective channel length than a planar MOSFET. In other words, the recess-channel MOSFET has an improved structure that diminishes difficulties caused by the short channel effect.
However, when the insulated gate electrode protrudes over a semiconductor substrate, the recess-channel MOSFET may preclude subsequent processes, such as, for example, the formation of a contact plug and a planarization process. Also, upper corners of the recessed channel region may cause the occurrence of leakage current due to a field crowding effect. Further, formation of the protruding gate electrode involves a very complicated patterning process.
In an attempt to overcome the above-mentioned difficulties, a semiconductor device having a buried word line was researched and is described in U.S. Pat. No. 6,770,535 B2, entitled “Semiconductor Integrated Circuit Device and Process for Manufacturing the Same”, by Yamada et al.
According to Yamada et al., a trench is formed across a channel region and an isolation layer. A word line is formed to fill a portion of the trench. An insulating pattern is formed to fill the remaining portion of the trench. As a result, the word line is buried underneath a semiconductor substrate. The buried word line provides a relatively longer effective channel length.
However, the effective channel width of the semiconductor device described in U.S. Pat. No. 6,770,535 B2 is dependent upon the channel region and the buried word line. Thus, the semiconductor device having the buried word line has substantially the same effective channel width as a planar MOSFET. As a result, the semiconductor device having the buried word line may be inferior to the planar MOSFET in current driving capability. For examples lowering of current driving capability may make it difficult to elevate the integration density of the semiconductor device.
Furthermore, the recess-channel MOSFET may have certain structural difficulties compared to the planar MOSFET in terms of a body effect, for example, an increase in threshold voltage.
In conclusion, there is a need in the art for an improved transistor and fabrication technique that adopt a buried word line and diminish the difficulties caused by a body effect.